A conventional digital filter includes first and second shifting sections which shift an input data IN1 of a first channel (hereinafter referred to as first channel data IN1) and an input data IN2 of a second channel (hereinafter referred to as second channel data IN2) in synchronization with the same clock signal CLK and hold them. The first and second shifting sections have multiple shift registers SR which are connected to each other in cascade. Output data of respective shift registers and the first and second channel data IN1 and IN2 are supplied to an input side of a multiplexer MUX.
The multiplexer MUX alternately selects and outputs output data of the first and second shifting sections in response to a level of the clock signal CLK, namely, “H” or “L” thereof, wherein an output side of the multiplexer MUX is connected to an FIR (Finite Impulse Response) filter section. The FIR filter section comprises multiple multipliers MUL for multiplying respective data outputted by the multiplexer MUX by filter coefficient, and multiple adders for adding the result of multiplication by the multiple multipliers. An output side of the FIR filter is connected to an output section.
The output section comprises two flip-flops FF and an inverter, and it holds output data of the FIR filter section in response to the clock signal CLK, and outputs output data OUT1, OUT2 relative to the first and second channels.
However, according to the conventional digital filter, it is necessary that the first and second channels have the same sampling frequency, and hence it is limited in the scope of application. Further, since the FIR filter section requires multiple multipliers and adders, and hence it has been desired to more simplify the scale of circuit.